1. Field of the Invention
This invention relates generally to minicomputing systems and more particularly to storage hierarchies having a high speed, low capacity storage device coupled to lower speed, high capacity storage devices.
2. Description of the Prior Art
The storage hierarchy concept is based on the phenomenon that individual stored program under execution exhibit the behavior that in a given period of time a localized area of memory receives a very high frequency of usage. Thus, a memory organization that provides a relatively small size buffer at the central processing unit (CPU) interface in addition and includes various levels of increasing capacity slower storage, can provide an effective access time that lies somewhere in between the range of the fastest and the slowest elements of the hierarchy and provides a large capacity memory system that is "transparent" to the software.
This invention takes advantage of a word organized memory. The prior art was limited to having no more than a minimal number of hardware registers which stored main memory addresses and data or instructions. When the need came about for expanded size, low cost high speed buffers, the prior art utilized a block organization.
U.S. Pat. No. 3,231,868 issued to L. Bloom et al. entitled "Memory Arrangement For Electronic Data Processing System" discloses a "look-aside" memory which stores a word in a register and its main memory address is an associated register. To improve performance over the Bloom et al. patent, the prior art went to the block transfer approach. Whenever a word was wanted of cache by the central processor, if that word was not in cache, a block of data including the desired word was sent to cache from main memory with the cache directory address location indicating the main memory address of that block.
An article by C. J. Conti entitled "Concepts for Buffer Storage" published by the IEEE Computer Group News, March, 1969, describes the transfer of 64 byte blocks as used on the IBM 360/85 when a particular byte not currently in the buffer is requested. The IBM 360/85 is described generally on pages 2 through 30 of the IBM System Journal, Volume 71, No. 1, 1968.
A general description of the System/370 Model 165 cache memory can be found on pages 214-220 of a book by Harry Katzen, Jr., entitled "Computer Organization and the System 370", published in 1971 by van Nostrand Reinhold Company, which describes a block transfer of 32 bytes between main storage and the buffer. U.S. Pat. No. 3,588,829 issued to Boland, et al., entitled "Integrated Memory System With Block Transfer To A Buffer Store", discloses the transfer of blocks of 8 words each. U.S. Pat. No. 3,896,419 issued to Lange, et al., entitled "Cache Memory Store In A Processor Of A Data Processing System" describes the transfer of blocks of 4 words each from main memory to cache. U.S. Pat. No. 3,820,078, issued to Curley, et al., entitled "Multilevel Storage Having A Buffer Store System With Variable Mapping Modes", describes the transfer of blocks of 32 bytes or half blocks of 16 bytes each from main memory to the buffer store.
In minicomputers, particularly those with an architecture which has all system units connected to a common bus, it has been found that block transfers of data between main memory and cache place too great a load on the system bus thereby reducing throughput of the overall system.